Dynamic random access memory (“DRAM”) cells are generally used in the art to store information. A DRAM cell may include a storage capacitor for storing information in the form of electric charges and a field-effect transistor for reading the electric charges. As semiconductor devices become more highly integrated, the area occupied by a storage capacitor is accordingly decreased, resulting in a decrease of capacitance. However, the capacitance required for a DRAM cell is fixed. One way to resolve the problem is to extend the height of the storage capacitor in order to increase its surface area. A trench capacitor is therefore introduced.
FIGS. 1A to 1D are diagrams showing a method in the art for manufacturing a silicon-insulator-silicon (“SIS”) trench capacitor. Referring to FIG. 1A, a trench 12 is formed in a semiconductor substrate 10 using a silicon nitride layer 16 as a mask and an oxide layer 14 as a pad layer. A buried plate 18 to serve as a first capacitor plate of the trench capacitor is formed at a lower region (not numbered) of trench 12. A dielectric layer 20 to serve as a capacitor dielectric of the trench capacitor is then formed along sidewalls (not numbered) of trench 12.
Referring to FIG. 1B, a first conductive layer 22 is filled in trench 12 and recessed to a level at the lower region, exposing a portion of dielectric layer 20. The exposed portion of dielectric layer 20 is removed. An oxide layer 24a is then deposited and annealed.
Referring to FIG. 1C, portions of oxide layer 24a are etched away to leave the remaining oxide layer 24b. A second conductive layer 26 is then filled in trench 12 and recessed, exposing a portion of the remaining oxide layer 24b. 
Referring to FIG. 1D, a collar oxide 24c is formed by etching away the exposed remaining oxide 24b. A collar oxide of a DRAM cell functions to prevent a leakage current from a diffused region, for example, a source or a drain, of a transistor of the DRAM cell to a buried plate. A third conductive layer 28 is then filled in trench 12 and recessed to form a buried strap. A buried strap functions to connect a trench capacitor of a DRAM cell to a transistor of the DRAM cell.
In the above-mentioned method, collar oxide 24c may be formed using a chemical vapor deposition (“CVD”) process, for example, a sub-atmospheric CVD (“SACVD”). Collar oxide 24c formed on the sidewalls of trench 12 by CVD disadvantageously results in a decrease of trench opening and a high series resistance. Furthermore, it is necessary for the above-mentioned method to etch away the remaining oxide layer 24b to prevent an oxide interface disposed between first conductive layer 22 and second conductive layer 26, which also disadvantageously results in a high series resistance.